1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of fabricating the semiconductor memory device, and this invention is applied, for example, to a NAND flash memory.
2. Description of the Related Art
In recent years, semiconductor memory devices, for example, NAND flash memories, have begun to be used as main memories of various electronic devices, such as portable audio devices, by virtue of their merits of large capacity and nonvolatility.
Under the circumstances, in addition to the enhancement in functions, the increase in memory capacity is a challenge to the NAND flash memory. The simplest method for realizing the increase in memory capacity is to promote microfabrication of memory cells. However, if the microfabrication of memory cells is advanced, the parasitic capacitance between floating gates (FG), which neighbor in a word line direction (i.e. the direction of wiring of control gates (CG)), increases, and consequently the coupling noise between the floating gates (FG) increases.
There is such a relationship that the width between the floating electrodes (FG) of memory cell transistors, which neighbor in the word line direction, is the sum of double the thickness of an inter-gate insulation film (IPD) and the remaining space width. For example, in the case of a 63 nm-generation NAND flash memory, the remaining space width is about 15 nm or less. In other words, even in the 63 nm-generation NAND flash memory, the space width, which is left after the formation of the inter-gate insulation film (IPD), is only less than 15 nm. The control gate (GC) that is a conductor is formed in the space width, thereby shielding the parasitic capacitance and reducing the coupling noise between the neighboring floating gates (FG).
However, if the 63 nm generation, for example, transitions to the next generation of finer structures, the width between floating gates (FG) neighboring in the word line direction will be smaller.
Consequently, the width between floating gates (FG) neighboring in the word line direction becomes less than double the physical film thickness of the inter-gate insulation film (IPD) and the width between the neighboring floating gates (FG) is entirely filled with the inter-gate insulation film (IPD).
Specifically, the structure in which the control electrode (CG) is put in the above-described space width cannot be realized, and a conductor for shielding is not present between the neighboring floating gates (FG). Consequently, since the parasitic capacitance between the floating gates (FG) increases, the coupling noise between the floating gates (FG) increases.
The coupling noise is proportional to the magnitude of the parasitic capacitance between the neighboring floating gates (FG). If the coupling noise is large, the voltage variation, which is imparted by the voltage variation of one of the neighboring floating gates (FG) to the other floating gate (FG), would increase.
If the coupling noise is considered, the width between the neighboring floating gates (FG) cannot be decreased and the microfabrication is restricted.
A document relating to the present invention is Jpn. Pat. Appln. KOKAI Publication No. 2005-277035.